;
; PCM1716 controler with AVR ATtiny26L
;
; ver 1.0 
; by UENO Tomohiro    20031022

.include	tn26def.inc

.def	tmp		= R16
.def	dac_md_h	= R17
.def	dac_md_l	= R18

.def	mode2		= R19
.def	mode3		= R20

.equ	dac_reset	= 7	; portB
.equ	dac_ml		= 6	; portB
.equ	dac_mc		= 5	; portB
.equ	dac_md		= 3	; portB
.equ	adc_in		= 4	; portB

	rjmp	reset	; $000 reset vector
	reti		; $001 EXT_INT0 
	reti		; $002 PIN_CHG 
	reti		; $003 TIMER1 COMPA 
	reti		; $004 TIMER1 COMPB
	reti		; $005 TIMER1 OVF1 
	reti		; $006 TIMER1 OVF0 
	reti		; $007 USI_STRT
	reti		; $008 USI_OVF
	reti		; $009 EE_RDY
	reti		; $00A ANA_COMP
	reti		; $00B ADC

reset	
	ldi	tmp, LOW(RAMEND)
	out	SP,tmp

	; portA initialize
	ldi	tmp,0b00000000	; input
	out	DDRA,tmp
	ldi	tmp,0b11110111	; bit 7-4,2-0 pullup
	out	PORTA,tmp

	; portB initialize
	ldi	tmp,0b11101000	; bit 7-5,3 output
	out	DDRB,tmp
	ldi	tmp,0x11101111	; bit 2-0 pullup
	out	PORTB,tmp

	; AD converter initialize
	ldi	tmp,0b00100111 	; REFS1=0,REFS0=0(AVCC),ADLAR=1(left adjust),convert=ADC7
	out	ADMUX,tmp

	ldi	tmp,0b11100111	; ADEN=1,ADSC=1,ADFR=1(continue),ADIF=0,ADIE=0,ASPS2-0=111
	out	ADCSR,tmp

	; PCM1716 reset
	cbi	PORTB,dac_reset
	nop
	nop
	sbi	PORTB,dac_reset

	; PCM1716 register set
	ldi	mode2,0b00000000
	ldi	mode3,0b00000100	; ope=0, mut=0, cko=0, rev=0, atc=1, lrp=0

	sbis	PINA,0			; iw0
	sbr	mode2,0b00001000

	sbis	PINA,1			; iw1
	sbr	mode2,0b00010000

	sbis	PINA,2			; iis
	sbr	mode3,0b00000001

	sbis	PINA,4			; dem
	sbr	mode2,0b00000010

	sbis	PINA,5			; sf0
	sbr	mode3,0b01000000

	sbis	PINA,6			; sf1
	sbr	mode3,0b10000000

	sbis	PINA,7			; sro
	sbr	mode3,0b00001000

	ldi	dac_md_h,0b00000100	; mode2 write
	mov	dac_md_l,mode2
	rcall	dac_write

	ldi	dac_md_h,0b00000110	; mode3 write, izd=0
	mov	dac_md_l,mode3
	rcall	dac_write

main_loop
	ldi	dac_md_h,(01)0x01
	in	dac_md_l,ADCH
	rcall	dac_write

	rjmp	main_loop

dac_write
	sbi	PORTB,dac_ml
	sbi	PORTB,dac_mc
	ldi	tmp,8
dac_write_loop_1
	cbi	PORTB,dac_md
	sbrc	dac_md_h,7
	sbi	PORTB,dac_md
	sbi	PORTB,dac_mc
	cbi	PORTB,dac_mc
	lsl	dac_md_h
	dec	tmp	
	brne	dac_write_loop_1
	ldi	tmp,7
dac_write_loop_2
	cbi	PORTB,dac_md
	sbrc	dac_md_l,7
	sbi	PORTB,dac_md
	sbi	PORTB,dac_mc
	cbi	PORTB,dac_mc
	lsl	dac_md_l
	dec	tmp	
	brne	dac_write_loop_2
	cbi	PORTB,dac_ml
	cbi	PORTB,dac_md
	sbrc	dac_md_l,7
	sbi	PORTB,dac_md
	sbi	PORTB,dac_mc
	sbi	PORTB,dac_ml
	cbi	PORTB,dac_mc
	ret